Specification Test Compaction for Analog Circuits and MEMS

Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies

Statistical Timing Based Optimization using Gate Sizing

Stochastic fuzzy controller

Stochastic Power Grid Analysis Considering Process Variations

Synchronization Processor Synthesis for Latency Insensitive Systems

Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI

Synthesis of Fault Tolerant Reversible Logic Circuits

Synthesis of Low-Power Digital Circuits Derived from Binary Decision Diagrams

Systematic Figure of Merit Computation for the Design of Pipeline ADC

Systematic Transaction Level Modeling of Embedded Systems with SystemC

SystemC Analysis of a New Dynamic Power Management Architecture

Systolic Arrays for Lattice-Reduction-Aided MIMO Detection

Techniques for Fast Transient Fault Grading Based on Autonomous Emulation

Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture

Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study

The Anatomy of the Grid - Enabling Scalable Virtual Organizations

The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture