Synchronization Processor Synthesis for Latency Insensitive Systems

Details Synchronization Processor Synthesis for Latency Insensitive Systems Synchronization Processor Synthesis for Latency Insensitive Systems

2007-10-25

arxiv.org/abs/0710.4659v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied. The main benefit of our approach is to preserve the local IP performances when encapsulating them and reduce SoC silicon area.

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