Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

Reduced-Latency SC Polar Decoder Architectures

Reliability-Centric High-Level Synthesis

Reliable System Specification for Self-Checking Data-Paths

Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

Reversible arithmetic logic unit

Reversible CAM Processor Modeled After Quantum Computer Behavior

Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits

Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Reversible Programmable Logic Array (RPLA) using Feynman & MUX Gates for Low Power Industrial Applications

Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications

RISC and CISC