On the Design and Analysis of Quaternary Serial and Parallel Adders
On the Information Engine of Circuit Design
On the operating unit size of load/store architectures
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
On Transformations of Load-Store Maurer Instruction Set Architecture
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Optimal Final Carry Propagate Adder Design for Parallel Multipliers
Optimal Memoryless Encoding for Low Power Off-Chip Data Buses
Optimized Generation of Data-Path from C Codes for FPGAs