Computer Science – Hardware Architecture
Scientific paper
2006-05-30
GRETSI'05 (Colloque sur le Traitement du Signal et de l'Image), Belgique (2005) 779-782
Computer Science
Hardware Architecture
Scientific paper
The design of complex Digital Signal Processing systems implies to minimize architectural cost and to maximize timing performances while taking into account communication and memory accesses constraints for the integration of dedicated hardware accelerator. Unfortunately, the traditional Matlab/ Simulink design flows gather not very flexible hardware blocs. In this paper, we present a methodology and a tool that permit the High-Level Synthesis of DSP applications, under both I/O timing and memory constraints. Based on formal models and a generic architecture, our tool GAUT helps the designer in finding a reasonable trade-off between the circuit's performance and its architectural complexity. The efficiency of our approach is demonstrated on the case study of a FFT algorithm.
Bomel Pierre
Corre Gwenolé
Coussy Philippe
Martin Eric
Senn Eric
No associations
LandOfFree
Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.
If you have personal experience with Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI will most certainly appreciate the feedback.
Profile ID: LFWR-SCP-O-467196