Lattice simulation on graphics cards
Leakage-Aware Interconnect for On-Chip Network
Limit on the Addressability of Fault-Tolerant Nanowire Decoders
Locality-Aware Process Scheduling for Embedded MPSoCs
Locally Served Network Computers
LOCKE Detailed Specification Tables
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
Logic, Design & Organization of PTVD-SHAM; A Parallel Time Varying & Data Super-helical Access Memory
Low Power Oriented CMOS Circuit Optimization Protocol
Low Power Shift and Add Multiplier Design
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
Low-Latency SC Decoder Architectures for Polar Codes