Techniques for Fast Transient Fault Grading Based on Autonomous Emulation
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
The Anatomy of the Grid - Enabling Scalable Virtual Organizations
The Distributed Network Processor: a novel off-chip and on-chip interconnection network architecture
The Integration of On-Line Monitoring and Reconfiguration Functions using EDAA - European design and Automation Association1149.4 Into a Safety Critical Automotive Electronic Control Unit
The LISA Pathfinder drift mode: implementation solutions for a robust algorithm
The NASA Exoplanet Science Institute Archives: KOA and NStED
Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)
Thermal-Aware Task Allocation and Scheduling for Embedded Systems
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit
Topics in asynchronous systems
Towards a Theory of Cache-Efficient Algorithms
Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations
Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures