Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

Details Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

2010-02-21

arxiv.org/abs/1002.3990v1

Computer Science

Hardware Architecture

4 pages

Scientific paper

For high throughput applications, turbo-like iterative decoders are implemented with parallel architectures. However, to be efficient parallel architectures require to avoid collision accesses i.e. concurrent read/write accesses should not target the same memory block. This consideration applies to the two main classes of turbo-like codes which are Low Density Parity Check (LDPC) and Turbo-Codes. In this paper we propose a methodology which finds a collision-free mapping of the variables in the memory banks and which optimizes the resulting interleaving architecture. Finally, we show through a pedagogical example the interest of our approach compared to state-of-the-art techniques.

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