A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13$μ$m Digital CMOS

A 97mW 110MS/s 12b Pipeline ADC Implemented in 0.18$μ$m Digital CMOS

A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

A Design Methodology for Space-Time Adapter

A Dual Digital Signal Processor VME Board For Instrumentation And Control Applications

A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs

A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs

A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design

A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture

A full-custom ASIC design of a 8-bit, 25 MHz, Pipeline ADC using 0.35 um CMOS technology

A handy systematic method for data hazards detection in an instruction set of a pipelined microprocessor

A hardware-software co-design approach to a JPEG encoder design for a planetary micro-rover application

A High Dynamic Range 3-Moduli-Set with Efficient Reverse Converter

A High-Level Reconfigurable Computing Platform Software Frameworks

A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware

A Light-Based Device for Solving the Hamiltonian Path Problem

A Memory Aware High Level Synthesis Too

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck

A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver

A Multicore Processor based Real-Time System for Automobile management application