Hard Data on Soft Errors: A Large-Scale Assessment of Real-World Error Rates in GPGPU
Hardware Accelerated Power Estimation
Hardware architectures for Successive Cancellation Decoding of Polar Codes
Hardware Implementation of Successive Cancellation Decoders for Polar Codes
Hardware Support for Arbitrarily Complex Loop Structures in Embedded Applications
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems
Hardware Trojan by Hot Carrier Injection
High Speed Multiple Valued Logic Full Adder Using Carbon Nano Tube Field Effect Transistor
High-level synthesis under I/O Timing and Memory constraints
HMTT: A Hybrid Hardware/Software Tracing System for Bridging Memory Trace's Semantic Gap
Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip