Systematic Transaction Level Modeling of Embedded Systems with SystemC

Details Systematic Transaction Level Modeling of Embedded Systems with SystemC Systematic Transaction Level Modeling of Embedded Systems with SystemC

2007-10-25

arxiv.org/abs/0710.4748v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

This paper gives an overview of a transaction level modeling (TLM) design flow for straightforward embedded system design with SystemC. The goal is to systematically develop both application-specific HW and SW components of an embedded system using the TLM approach, thus allowing for fast communication architecture exploration, rapid prototyping and early embedded SW development. To this end, we specify the lightweight transaction-based communication protocol SHIP and present a methodology for automatic mapping of the communication part of a system to a given architecture, including HW/SW interfaces.

Affiliated with

Also associated with

No associations

Rating

Systematic Transaction Level Modeling of Embedded Systems with SystemC does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.

If you have personal experience with Systematic Transaction Level Modeling of Embedded Systems with SystemC, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systematic Transaction Level Modeling of Embedded Systems with SystemC will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFWR-SCP-O-432345