Data-stationary Architecture to Execute Quantum Algorithms Classically
Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs
Decoding the Golden Code: a VLSI design
Decting Errors in Reversible Circuits With Invariant Relationships
Defragmenting the Module Layout of a Partially Reconfigurable Device
Design and ASIC implementation of DUC/DDC for communication systems
Design and Implementation of MPICH2 over InfiniBand with RDMA Support
Design and Simulation of an 8-bit Dedicated Processor for calculating the Sine and Cosine of an Angle using the CORDIC Algorithm
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer
Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips
Design of multimedia processor based on metric computation
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters
Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip
Difficulties in the Implementation of Quantum Computers
DPA on quasi delay insensitive asynchronous circuits: formalization and improvement
DVS for On-Chip Bus Designs Based on Timing Error Correction
DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices