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Data-stationary Architecture to Execute Quantum Algorithms Classically

Computer Science – Hardware Architecture
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Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs

Computer Science – Hardware Architecture
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Decoding the Golden Code: a VLSI design

Computer Science – Hardware Architecture
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Decting Errors in Reversible Circuits With Invariant Relationships

Computer Science – Hardware Architecture
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Defragmenting the Module Layout of a Partially Reconfigurable Device

Computer Science – Hardware Architecture
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Design and ASIC implementation of DUC/DDC for communication systems

Computer Science – Hardware Architecture
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Design and Implementation of MPICH2 over InfiniBand with RDMA Support

Computer Science – Hardware Architecture
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Design and Simulation of an 8-bit Dedicated Processor for calculating the Sine and Cosine of an Angle using the CORDIC Algorithm

Computer Science – Hardware Architecture
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Design of a Virtual Component Neutral Network-on-Chip Transaction Layer

Computer Science – Hardware Architecture
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Design of Fault-Tolerant and Dynamically-Reconfigurable Microfluidic Biochips

Computer Science – Hardware Architecture
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Design of multimedia processor based on metric computation

Computer Science – Hardware Architecture
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Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

Computer Science – Hardware Architecture
Scientific paper

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Designing a WISHBONE Protocol Network Adapter for an Asynchronous Network-on-Chip

Computer Science – Hardware Architecture
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Difficulties in the Implementation of Quantum Computers

Computer Science – Hardware Architecture
Scientific paper

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DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

Computer Science – Hardware Architecture
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DVS for On-Chip Bus Designs Based on Timing Error Correction

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DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices

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