Synthesis of Fault Tolerant Reversible Logic Circuits

Details Synthesis of Fault Tolerant Reversible Logic Circuits Synthesis of Fault Tolerant Reversible Logic Circuits

2010-08-19

arxiv.org/abs/1008.3340v1

IEEE International Conference on Testing and Diagnosis, 28-29 April, 2009, Chengdu, China

Computer Science

Hardware Architecture

4 pages, 9 figures, 7 tables

Scientific paper

10.1109/CAS-ICTD.2009.4960883

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 universal reversible logic gate, IG. It is a parity preserving reversible logic gate, that is, the parity of the inputs matches the parity of the outputs. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Finally, it is shown how a fault tolerant reversible full adder circuit can be realized using only two IGs. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

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