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Scalability Terminology: Farms, Clones, Partitions, Packs, RACS and RAPS

Computer Science – Hardware Architecture
Scientific paper

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ScotGrid: A Prototype Tier 2 Centre

Computer Science – Hardware Architecture
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Simultaneous Reduction of Dynamic and Static Power in Scan Structures

Computer Science – Hardware Architecture
Scientific paper

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Smart Temperature Sensor for Thermal Testing of Cell-Based ICs

Computer Science – Hardware Architecture
Scientific paper

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SNS Timing System

Computer Science – Hardware Architecture
Scientific paper

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SoC Software Components Diagnosis Technology

Computer Science – Hardware Architecture
Scientific paper

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SOC Testing Methodology and Practice

Computer Science – Hardware Architecture
Scientific paper

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Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Computer Science – Hardware Architecture
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Solving the Hamiltonian path problem with a light-based computer

Computer Science – Hardware Architecture
Scientific paper

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Solving the subset-sum problem with a light-based device

Computer Science – Hardware Architecture
Scientific paper

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Sorting Network for Reversible Logic Synthesis

Computer Science – Hardware Architecture
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Specification Test Compaction for Analog Circuits and MEMS

Computer Science – Hardware Architecture
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Static Address Generation Easing: a Design Methodology for Parallel Interleaver Architectures

Computer Science – Hardware Architecture
Scientific paper

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Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies

Computer Science – Hardware Architecture
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Statistical Timing Based Optimization using Gate Sizing

Computer Science – Hardware Architecture
Scientific paper

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Stochastic fuzzy controller

Computer Science – Hardware Architecture
Scientific paper

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Stochastic Power Grid Analysis Considering Process Variations

Computer Science – Hardware Architecture
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Synchronization Processor Synthesis for Latency Insensitive Systems

Computer Science – Hardware Architecture
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Synthèse Comportementale Sous Contraintes de Communication et de Placement Mémoire pour les composants du TDSI

Computer Science – Hardware Architecture
Scientific paper

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Synthesis of Fault Tolerant Reversible Logic Circuits

Computer Science – Hardware Architecture
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