Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

Optimized Generation of Data-Path from C Codes for FPGAs

Partial Reversible Gates(PRG) for Reversible BCD Arithmetic

Performance of Cache Memory Subsystems for Multicore Architectures

Performance-Optimum Superscalar Architecture for Embedded Applications

Physarum machine: Implementation of Kolmogorov-Uspensky machine in biological substrat

picoArray Technology: The Tool's Story

Platform Based Design for Automotive Sensor Conditioning

Policies of System Level Pipeline Modeling

Power comparison of CMOS and adiabatic full adder circuit

Power optimized programmable embedded controller

Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage

Pseudo-Ring Testing Schemes and Algorithms of RAM Built-In and Embedded Self-Testing

Quantum Algorithm Processor For Finding Exact Divisors

Quantum Algorithm Processors to Reveal Hamiltonian Cycles

Quantum Cost Efficient Reversible BCD Adder for Nanotechnology Based Systems

Queue Management in Network Processors

Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

Reduced-Latency SC Polar Decoder Architectures

Reliability-Centric High-Level Synthesis