Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

Details Optimal Memoryless Encoding for Low Power Off-Chip Data Buses Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

2007-12-17

arxiv.org/abs/0712.2640v1

Computer Science

Hardware Architecture

Proceedings of the 2006 IEEE/ACM international Conference on Computer-Aided Design (San Jose, California, November 05 - 09, 20

Scientific paper

10.1145/1233501.1233575

Off-chip buses account for a significant portion of the total system power consumed in embedded systems. Bus encoding schemes have been proposed to minimize power dissipation, but none has been demonstrated to be optimal with respect to any measure. In this paper, we give the first provably optimal and explicit (polynomial-time constructible) families of memoryless codes for minimizing bit transitions in off-chip buses. Our results imply that having access to a clock does not make a memoryless encoding scheme that minimizes bit transitions more powerful.

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