Pseudo-Ring Testing Schemes and Algorithms of RAM Built-In and Embedded Self-Testing

Details Pseudo-Ring Testing Schemes and Algorithms of RAM Built-In and Embedded Self-Testing Pseudo-Ring Testing Schemes and Algorithms of RAM Built-In and Embedded Self-Testing

2011-06-18

arxiv.org/abs/1106.3677v1

14 th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 13-15, 2011, Cottbus, Germany

Computer Science

Hardware Architecture

4 pages

Scientific paper

Scan and ring schemes of the pseudo-ring memory selftesting are investigated. Both schemes are based on emulation of the linear or nonlinear feedback shift register by memory itself. Peculiarities of the pseudo-ring schemes implementation for multi-port and embedded memories, and for register file are described. It is shown that only small additional logic is required and allows microcontrollers at-speed testing. Also, in this article,are given the a posteriori values of some type of memories faults coverage when pseudo-ring testing schemes are applied.

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