Power optimized programmable embedded controller

Details Power optimized programmable embedded controller Power optimized programmable embedded controller

2010-09-09

arxiv.org/abs/1009.1796v1

International Journal of Computer Networks & Communications (IJCNC),Vol.2, No.4, July 2010

Computer Science

Hardware Architecture

11 pages,11 figures,International Journal Publication

Scientific paper

10.5121/ijcnc.2010.2409

Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functionality. Clock-gating is the most common technique used for reducing processor's power. In this work clock gating technique is applied to optimize the power of fully programmable Embedded Controller (PEC) employing RISC architecture. The CPU designed supports i) smart instruction set, ii) I/O port, UART iii) on-chip clocking to provide a range of frequencies , iv) RISC as well as controller concepts. The whole design is captured using VHDL and is implemented on FPGA chip using Xilinx .The architecture and clock gating technique together is found to reduce the power consumption by 33.33% of total power consumed by this chip.

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