Computer Science – Hardware Architecture
Scientific paper
2007-10-25
Dans Design, Automation and Test in Europe | Designers'Forum - DATE'05, Munich : Allemagne (2005)
Computer Science
Hardware Architecture
Submitted on behalf of EDAA (http://www.edaa.com/)
Scientific paper
One of the main bottlenecks when designing a network processing system is very often its memory subsystem. This is mainly due to the state-of-the-art network links operating at very high speeds and to the fact that in order to support advanced Quality of Service (QoS), a large number of independent queues is desirable. In this paper we analyze the performance bottlenecks of various data memory managers integrated in typical Network Processing Units (NPUs). We expose the performance limitations of software implementations utilizing the RISC processing cores typically found in most NPU architectures and we identify the requirements for hardware assisted memory management in order to achieve wire-speed operation at gigabit per second rates. Furthermore, we describe the architecture and performance of a hardware memory manager that fulfills those requirements. This memory manager, although it is implemented in a reconfigurable technology, it can provide up to 6.2Gbps of aggregate throughput, while handling 32K independent queues.
Kachris C.
Kornaros G.
Mavroidis I.
Nikologiannis A.
Orphanoudakis T.
No associations
LandOfFree
Queue Management in Network Processors does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.
If you have personal experience with Queue Management in Network Processors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Queue Management in Network Processors will most certainly appreciate the feedback.
Profile ID: LFWR-SCP-O-432771