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Multi-Amdahl: Optimal Resource Sharing with Multiple Program Execution Segments

Computer Science – Hardware Architecture
Scientific paper

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Multi-core processors - An overview

Computer Science – Hardware Architecture
Scientific paper

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Multi-core: Adding a New Dimension to Computing

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Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis

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Multi-standard programmable baseband modulator for next generation wireless communication

Computer Science – Hardware Architecture
Scientific paper

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MultiNoC: A Multiprocessing System Enabled by a Network on Chip

Computer Science – Hardware Architecture
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Multiplierless Modules for Forward and Backward Integer Wavelet Transform

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Nature-Inspired Interconnects for Self-Assembled Large-Scale Network-on-Chip Designs

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New Perspectives and Opportunities From the Wild West of Microelectronic Biochips

Computer Science – Hardware Architecture
Scientific paper

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New Schemes for Self-Testing RAM

Computer Science – Hardware Architecture
Scientific paper

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Noise Limited Computational Speed

Computer Science – Hardware Architecture
Scientific paper

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Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format

Computer Science – Hardware Architecture
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Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU

Computer Science – Hardware Architecture
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On the Design and Analysis of Quaternary Serial and Parallel Adders

Computer Science – Hardware Architecture
Scientific paper

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On the Information Engine of Circuit Design

Computer Science – Hardware Architecture
Scientific paper

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On the operating unit size of load/store architectures

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Scientific paper

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On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs

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On Transformations of Load-Store Maurer Instruction Set Architecture

Computer Science – Hardware Architecture
Scientific paper

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On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips

Computer Science – Hardware Architecture
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Optimal Final Carry Propagate Adder Design for Parallel Multipliers

Computer Science – Hardware Architecture
Scientific paper

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