On the Design and Analysis of Quaternary Serial and Parallel Adders

Details On the Design and Analysis of Quaternary Serial and Parallel Adders On the Design and Analysis of Quaternary Serial and Parallel Adders

2010-09-14

arxiv.org/abs/1009.2622v1

Computer Science

Hardware Architecture

Scientific paper

Optimization techniques for decreasing the time and area of adder circuits have been extensively studied for years mostly in binary logic system. In this paper, we provide the necessary equations required to design a full adder in quaternary logic system. We develop the equations for single-stage parallel adder which works as a carry look-ahead adder. We also provide the design of a logarithmic stage parallel adder which can compute the carries within log2(n) time delay for n qudits. At last, we compare the designs and finally propose a hybrid adder which combines the advantages of serial and parallel adder.

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