On the operating unit size of load/store architectures

Details On the operating unit size of load/store architectures On the operating unit size of load/store architectures

2007-11-06

arxiv.org/abs/0711.0838v2

Mathematical Structures in Computer Science, 20(3):395--417, 2010

Computer Science

Hardware Architecture

23 pages; minor errors corrected, explanations added, references replaced

Scientific paper

10.1017/S0960129509990314

We introduce a strict version of the concept of a load/store instruction set architecture in the setting of Maurer machines. We take the view that transformations on the states of a Maurer machine are achieved by applying threads as considered in thread algebra to the Maurer machine. We study how the transformations on the states of the main memory of a strict load/store instruction set architecture that can be achieved by applying threads depend on the operating unit size, the cardinality of the instruction set, and the maximal number of states of the threads.

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