Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format

Details Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format

2006-03-22

arxiv.org/abs/cs/0603088v1

Computer Science

Hardware Architecture

6 Pages: This paper is a corrected version of our recent publication published in 19th International Conference on VLSI Design

Scientific paper

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel BCD adders called carry skip and carry look-ahead BCD adders respectively. Furthermore, in the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology, and optical computing. It is not possible to realize quantum computing without reversible logic. Thus, this paper also paper provides the reversible logic implementation of the conventional BCD adder as the well as the proposed Carry Skip BCD adder using a recently proposed TSG gate. Furthermore, a new reversible gate called TS-3 is also being proposed and it has been shown that the proposed reversible logic implementation of the BCD Adders is much better compared to recently proposed one, in terms of number of reversible gates used and garbage outputs produced. The reversible BCD circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU.

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