Limit on the Addressability of Fault-Tolerant Nanowire Decoders

Locality-Aware Process Scheduling for Embedded MPSoCs

Locally Served Network Computers

LOCKE Detailed Specification Tables

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Logic, Design & Organization of PTVD-SHAM; A Parallel Time Varying & Data Super-helical Access Memory

Low Power Oriented CMOS Circuit Optimization Protocol

Low Power Shift and Add Multiplier Design

Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

Low-Latency SC Decoder Architectures for Polar Codes

Maintaining Virtual Areas on FPGAs using Strip Packing with Delays

Meeting the Embedded Design Needs of Automotive Applications

Memory Aware High-Level Synthesis for Embedded Systems

Memory Testing Under Different Stress Conditions: An Industrial Evaluation

Memristor-based Circuits for Performing Basic Arithmetic Operations

Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels

Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits

Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction

Modeling of a Reconfigurable OFDM IP Block Family For an RF System Simulator

Modeling the Non-Linear Behavior of Library Cells for an Accurate Static Noise Analysis