Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

Details Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

2007-10-25

arxiv.org/abs/0710.4763v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

This paper addresses delay test for SOC devices with high frequency clock
domains. A logic design for on-chip high-speed clock generation, implemented to
avoid expensive test equipment, is described in detail. Techniques for on-chip
clock generation, meant to reduce test vector count and to increase test
quality, are discussed. ATPG results for the proposed techniques are given.

Affiliated with

Also associated with

No associations

Rating

Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.

If you have personal experience with Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFWR-SCP-O-432406