Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

Details Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL

2007-10-25

arxiv.org/abs/0710.4761v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially available components to keep costs low, yet achieves performance characteristics comparable to (and in some ways exceeding) more expensive ATE. A common CMOS FPGA-based logic core provides flexibility, adaptability, and communication with controlling computers while customized positive emitter-coupled logic (PECL) achieves multi-gigahertz data rates with about $\pm$25ps timing accuracy.

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