A Memory Aware High Level Synthesis Too

Details A Memory Aware High Level Synthesis Too A Memory Aware High Level Synthesis Too

2006-05-30

arxiv.org/abs/cs/0605144v1

International Symposium on VLSI (2004) 279-280

Computer Science

Hardware Architecture

ISBN 0-7695-2097-9

Scientific paper

We introduce a new approach to take into account the memory architecture and the memory mapping in High- Level Synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping file to include those memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.

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