Computer Science – Hardware Architecture
Scientific paper
2007-06-12
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS) (28/05/2007) 2946
Computer Science
Hardware Architecture
ISBN:1-4244-0921-7
Scientific paper
This paper presents a solution to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall architecture of the system is significantly affected by communication architecture, so the designers need specifically optimized adapters. By explicitly modeling these communications within an effective graph-theoretic model and analysis framework, we automatically generate an optimized architecture, named Space-Time AdapteR (STAR). Our design flow inputs a C description of Input/Output data scheduling, and user requirements (throughput, latency, parallelism...), and formalizes communication constraints through a Resource Constraints Graph (RCG). The RCG properties enable an efficient architecture space exploration in order to synthesize a STAR component. The proposed approach has been tested to design an industrial data mixing block example: an Ultra-Wideband interleaver.
Chavet Cyrille
Coussy Philippe
Martin Eric
Urard Pascal
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