A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

Details A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices A Design Methodology for Folded, Pipelined Architectures in VLSI Applications using Projective Space Lattices

2011-08-19

arxiv.org/abs/1108.3970v1

Computer Science

Hardware Architecture

To be submitted to Elsevier Journal of Microprocessors and Microsystems: Embedded Hardware Design

Scientific paper

Semi-parallel, or folded, VLSI architectures are used whenever hardware resources need to be saved at design time. Most recent applications that are based on Projective Geometry (PG) based balanced bipartite graph also fall in this category. In this paper, we provide a high-level, top-down design methodology to design optimal semi-parallel architectures for applications, whose Data Flow Graph (DFG) is based on PG bipartite graph. Such applications have been found e.g. in error-control coding and matrix computations. Unlike many other folding schemes, the topology of connections between physical elements does not change in this methodology. Another advantage is the ease of implementation. To lessen the throughput loss due to folding, we also incorporate a pipelining strategy in the design methodology. A complete decoder has been prototyped for proof of concept, and is publicly available. Another specific high-performance design of an LDPC decoder based on this methodology was worked out in past, and has been patented as well.

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