Computer Science – Hardware Architecture
Scientific paper
Jan 2011
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2011spie.7878e..28s&link_type=abstract
Intelligent Robots and Computer Vision XXVIII: Algorithms and Techniques. Edited by Röning, Juha; Casasent, David P.; Hall, Ern
Computer Science
Hardware Architecture
Scientific paper
Micro-rovers aimed with the objective of planetary exploration of moons and heavenly bodies are becoming focus of many space missions. These micro-rover missions face hard challenges of harsh environment and resource constraints such as power and transmission bandwidth. The image data collected by the on-board cameras are often not possible to transmit to ground due to low bandwidth or adequate transmission duration. The JPEG image compression standard that is developed by the Joint Photographic Experts Group committee for use in compressing digital images and full color photographic images is ubiquitous and is a useful solution to the problem. In this paper, a hardware-software based co-design approach is presented with the aim to implement a JPEG encoder for reducing the transmission bandwidth requirement of a planetary micro-rover. A pipelined hardware architecture of the JPEG encoder requiring reduced hardware resources and power is designed for PowerPC and MIL-1750 processor interface and its performance and resource utilization using standard images of various sizes and quality settings for both these processor architecture is compared. Results are substantiated using extensive simulation and RTL implementation in FPGA. Based on these studies an efficient architecture is arrived at for use in a planetary microrover for future exploration by an Indian moon mission.
Bhardwaj K. M.
Malik Naveen Kr.
Parameswaran K.
Sarma Samar Sen
Udupa S.
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