A handy systematic method for data hazards detection in an instruction set of a pipelined microprocessor

Details A handy systematic method for data hazards detection in an instruction set of a pipelined microprocessor A handy systematic method for data hazards detection in an instruction set of a pipelined microprocessor

2012-03-04

arxiv.org/abs/1203.0787v1

Computer Science

Hardware Architecture

7 pages, 10 figures, 9 tables

Scientific paper

It is intended in this document to introduce a handy systematic method for enumerating all possible data dependency cases that could occur between any two instructions that might happen to be processed at the same time at different stages of the pipeline. Given instructions of the instruction set, specific information about operands of each instruction and when an instruction reads or writes data, the method could be used to enumerate all possible data hazard cases and to determine whether forwarding or stalling is suitable for resolving each case.

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