A New Design for Array Multiplier with Trade off in Power and Area
A New Embedded Measurement Structure for eDRAM Capacitor
A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
A Novel Methodology for Thermal Analysis & 3-Dimensional Memory Integration
A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices
A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
A Resolution for Shared Memory Conflict in Multiprocessor System-on-a-Chip
A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding
A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback
A Self-Reconfigurable Computing Platform Hardware Architecture
A Simulation Experiment on a Built-In Self Test Equipped with Pseudorandom Test Pattern Generator and Multi-Input Shift Register (MISR)
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning
A Unique 10 Segment Display for Bengali Numerals
A VLSI Design Flow for Secure Side-Channel Attack Resistant ICs
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors
Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System
Adaptive Domain Model: Dealing With Multiple Attributes of Self-Managing Distributed Object Systems