A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding

Details A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding

2009-10-18

arxiv.org/abs/0910.3427v4

IEEE Transactions on Circuits and Systems-Part II: Express Briefs, vol. 57, no. 9, pp. 706-710, Sep 2010

Computer Science

Hardware Architecture

Accepted for IEEE Transactions on Circuits and Systems II Express Briefs, May 2010. This draft from April 2010 will not be upd

Scientific paper

10.1109/TCSII.2010.2056014

Multiple-input multiple-output (MIMO) wireless transmission imposes huge challenges on the design of efficient hardware architectures for iterative receivers. A major challenge is soft-input soft-output (SISO) MIMO demapping, often approached by sphere decoding (SD). In this paper, we introduce the - to our best knowledge - first VLSI architecture for SISO SD applying a single tree-search approach. Compared with a soft-output-only base architecture similar to the one proposed by Studer et al. in IEEE J-SAC 2008, the architectural modifications for soft input still allow a one-node-per-cycle execution. For a 4x4 16-QAM system, the area increases by 57% and the operating frequency degrades by 34% only.

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