Computer Science – Hardware Architecture
Scientific paper
2010-08-20
Computer Science
Hardware Architecture
7 pages, 12 figures, 1 table
Scientific paper
Reversible logic has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its applications in low power CMOS design, cryptography, optical information processing and nanotechnology. This paper presents a novel and quantum cost efficient reversible full adder gate in nanotechnology. This gate can work singly as a reversible full adder unit and requires only one clock cycle. The proposed gate is a universal gate in the sense that it can be used to synthesize any arbitrary Boolean functions. It has been demonstrated that the hardware complexity offered by the proposed gate is less than the existing counterparts. The proposed reversible full adder gate also adheres to the theoretical minimum established by the researchers.
No associations
LandOfFree
A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.
If you have personal experience with A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and A Novel Quantum Cost Efficient Reversible Full Adder Gate in Nanotechnology will most certainly appreciate the feedback.
Profile ID: LFWR-SCP-O-81240