Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System

Details Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System Accelerating Algorithms using a Dataflow Graph in a Reconfigurable System

2011-10-17

arxiv.org/abs/1110.3655v1

Computer Science

Hardware Architecture

13 pages, 8 figures, 1 listing, 1 algorithm, 1 Table

Scientific paper

In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates. The results of benchmarks implemented using the static dataflow architecture are reported at the end of this paper.

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