A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices

Details A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices

2005-03-24

arxiv.org/abs/cs/0503066v1

Computer Science

Hardware Architecture

7 pages, 7 figures, 2 tables, Latex, to appear in International Workshop on Rapid System Prototyping (RSP 2005)

Scientific paper

Management of communication by on-line routing in new FPGAs with a large amount of logic resources and partial reconfigurability is a new challenging problem. A Network-on-Chip (NoC) typically uses packet routing mechanism, which has often unsafe data transfers, and network interface overhead. In this paper, circuit routing for such dynamic NoCs is investigated, and a practical 1-dimensional network with an efficient routing algorithm is proposed and implemented. Also, this concept has been extended to the 2-dimensional case. The implementation results show the low area overhead and high performance of this network.

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