Associative control processor with a rigid structure

Associative Memory For Reversible Programming and Charge Recovery

Asynchronous logic circuits and sheaf obstructions

At-Speed Logic BIST for IP Cores

Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis

Boosting XML Filtering with a Scalable FPGA-based Architecture

Brain-like infrastructure for embedded SoC diagnosis

Bright-Field AAPSM Conflict Detection and Correction

BSSSN: Bit String Swapping Sorting Network for Reversible Logic Synthesis

Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip

Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings

C Based Hardware Design for Wireless Applications

C-slow Technique vs Multiprocessor in designing Low Area Customized Instruction set Processor for Embedded Applications

CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming

Cantilever-Based Biosensors in CMOS Technology

Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown

CMOS-Based Biosensor Arrays

Combinational Logic Circuit Design with the Buchberger Algorithm

Combined Integer and Floating Point Multiplication Architecture(CIFM) for FPGAs and Its Reversible Logic Implementation

Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs