Computer Science – Hardware Architecture
Scientific paper
2010-08-27
Journal of Computer Science (IBAIS University), Vol. 1, No. 1, pp. 94-99, 2007
Computer Science
Hardware Architecture
8 pages, 11 figures, 2 tables
Scientific paper
In this paper, we have introduced the notion of UselessGate and ReverseOperation. We have also given an algorithm to implement a sorting network for reversible logic synthesis based on swapping bit strings. The network is constructed in terms of n*n Toffoli Gates read from left to right and it has shown that there will be no more gates than the number of swappings the algorithm requires. The gate complexity of the network is O(n2). The number of gates in the network can be further reduced by template reduction technique and removing UselessGate from the network.
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