Computer Science – Hardware Architecture
Scientific paper
2011-05-10
IEEE International Conference on Automation Quality and Testing Robotics (AQTR), 28-30 May 2010, Cluj-Napoca, Romania
Computer Science
Hardware Architecture
5 pages
Scientific paper
This article describes high-speed multiprocessor architecture for the concurrent analyzing information represented in analytic, graph- and table forms of associative relations to search, recognize and make a decision in n-dimensional vector discrete space. Vector-logical process models of actual applications,for which the quality of solution is estimated by the proposed integral non-arithmetical metric of the interaction between Boolean vectors, are described.
gharibi Wajeb
Guz Olesya
Hahanov Vladimir
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