Sorting Network for Reversible Logic Synthesis

Details Sorting Network for Reversible Logic Synthesis Sorting Network for Reversible Logic Synthesis

2010-08-22

arxiv.org/abs/1008.3694v1

International Conference for Upcoming Engineers, Windsor University, Ontario, Canada, May 20-21, 2005

Computer Science

Hardware Architecture

4 pages, 8 figures, 2 tables

Scientific paper

In this paper, we have introduced an algorithm to implement a sorting network for reversible logic synthesis based on swapping bit strings. The algorithm first constructs a network in terms of n*n Toffoli gates read from left to right. The number of gates in the circuit produced by our algorithm is then reduced by template matching and removing useless gates from the network. We have also compared the efficiency of the proposed method with the existing ones.

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