Computer Science – Hardware Architecture
Scientific paper
2011-06-18
Proceedings of IEEE, East-West Design & Test, Symposium (EWDTS'08),Lviv, Ukraine, October 9 - 12, 2008
Computer Science
Hardware Architecture
4 pages
Scientific paper
A novel approach to evaluation of hardware and software testability,
represented in the form of register transfer graph, is proposed. Instances of
making of software graph models for their subsequent testing and diagnosis are
shown.
Chumachenko Svetlana
gharibi Wajeb
Hahanova Anna
Sushanov Aleksey
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