Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

Details Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

2007-10-25

arxiv.org/abs/0710.4722v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 $\mu$m CMOS process.

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