Computer Science – Hardware Architecture
Scientific paper
2012-03-19
IJCSI International Journal of Computer Science Issues, Vol. 8, Issue 4, No 2, July 2011, 262-268
Computer Science
Hardware Architecture
7 pages, 6 figures; ISSN (Online): 1694-0814
Scientific paper
The Scaling of microchip technologies, from micron to submicron and now to deep sub-micron (DSM) range, has enabled large scale systems-on-chip (SoC). In future deep submicron (DSM) designs, the interconnect effect will definitely dominate performance. Network-on-Chip (NoC) has become a promising solution to bus-based communication infrastructure limitations. NoC designs usually targets Application Specific Integrated Circuits (ASICs), however, the fabrication process costs a lot. Implementing a NoC on an FPGA does not only reduce the cost but also decreases programming and verification cycles. In this paper, an Asynchronous NoC has been implemented on a SPARTAN-3E\textregistered device. The NoC supports basic transactions of both widely used on-chip interconnection standards, the Open Core Protocol (OCP) and the WISHBONE Protocol. Although, FPGA devices are synchronous in nature, it has been shown that they can be used to prototype a Global Asynchronous Local Synchronous (GALS) systems, comprising an Asynchronous NoC connecting IP cores operating in different clock domains.
El-Bably M.
Keshk Hesham M. A. M.
Saad E. M.
Soliman Ahmed H. M.
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