DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

Details DPA on quasi delay insensitive asynchronous circuits: formalization and improvement DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

2007-10-18

arxiv.org/abs/0710.3443v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

10.1109/DATE.2005.124

The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.

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