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Reliable System Specification for Self-Checking Data-Paths

Computer Science – Hardware Architecture
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Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

Computer Science – Hardware Architecture
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Reversible arithmetic logic unit

Computer Science – Hardware Architecture
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Reversible CAM Processor Modeled After Quantum Computer Behavior

Computer Science – Hardware Architecture
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Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits

Computer Science – Hardware Architecture
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Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Computer Science – Hardware Architecture
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Reversible Programmable Logic Array (RPLA) using Feynman & MUX Gates for Low Power Industrial Applications

Computer Science – Hardware Architecture
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Reversible Programmable Logic Array (RPLA) using Fredkin & Feynman Gates for Industrial Electronics and Applications

Computer Science – Hardware Architecture
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RISC and CISC

Computer Science – Hardware Architecture
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Scalability Terminology: Farms, Clones, Partitions, Packs, RACS and RAPS

Computer Science – Hardware Architecture
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ScotGrid: A Prototype Tier 2 Centre

Computer Science – Hardware Architecture
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Simultaneous Reduction of Dynamic and Static Power in Scan Structures

Computer Science – Hardware Architecture
Scientific paper

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Smart Temperature Sensor for Thermal Testing of Cell-Based ICs

Computer Science – Hardware Architecture
Scientific paper

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SNS Timing System

Computer Science – Hardware Architecture
Scientific paper

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SoC Software Components Diagnosis Technology

Computer Science – Hardware Architecture
Scientific paper

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SOC Testing Methodology and Practice

Computer Science – Hardware Architecture
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Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits

Computer Science – Hardware Architecture
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Solving the Hamiltonian path problem with a light-based computer

Computer Science – Hardware Architecture
Scientific paper

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Solving the subset-sum problem with a light-based device

Computer Science – Hardware Architecture
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Sorting Network for Reversible Logic Synthesis

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