Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Details Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

2010-08-19

arxiv.org/abs/1008.3288v1

Bangladesh Academy of Science Journal, Vol. 32, No. 2, pp. 193-200, December 2008

Computer Science

Hardware Architecture

9 pages, 7 figures, 5 tables

Scientific paper

10.3329/jbas.v32i2.2431

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

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