Computer Science – Hardware Architecture
Scientific paper
2007-10-25
Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)
Computer Science
Hardware Architecture
Submitted on behalf of EDAA (http://www.edaa.com/)
Scientific paper
The design of reliable circuits has received a lot of attention in the past, leading to the definition of several design techniques introducing fault detection and fault tolerance properties in systems for critical applications/environments. Such design methodologies tackled the problem at different abstraction levels, from switch-level to logic, RT level, and more recently to system level. Aim of this paper is to introduce a novel system-level technique based on the redefinition of the operators functionality in the system specification. This technique provides reliability properties to the system data path, transparently with respect to the designer. Feasibility, fault coverage, performance degradation and overheads are investigated on a FIR circuit.
Bolchini C.
Pomante L.
Salice F.
Sciuto D.
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