Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

Details Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures Turbo NOC: a framework for the design of Network On Chip based turbo decoder architectures

2009-09-10

arxiv.org/abs/0909.1876v1

Computer Science

Hardware Architecture

submitted to IEEE Trans. on Circuits and Systems I (submission date 27 may 2009)

Scientific paper

This work proposes a general framework for the design and simulation of network on chip based turbo decoder architectures. Several parameters in the design space are investigated, namely the network topology, the parallelism degree, the rate at which messages are sent by processing nodes over the network and the routing strategy. The main results of this analysis are: i) the most suited topologies to achieve high throughput with a limited complexity overhead are generalized de-Bruijn and generalized Kautz topologies; ii) depending on the throughput requirements different parallelism degrees, message injection rates and routing algorithms can be used to minimize the network area overhead.

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