Computer Science – Hardware Architecture
Scientific paper
2007-10-25
Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)
Computer Science
Hardware Architecture
Submitted on behalf of EDAA (http://www.edaa.com/)
Scientific paper
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the concept. VHDL modeling provides extensive verification of the topology. Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing. We present two practical examples of possible design improvements analyzed and implemented with this methodology.
Atarodi Mojtaba
Leblebici Yusuf
Müller Paul
Tajalli Armin
No associations
LandOfFree
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.
If you have personal experience with Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit will most certainly appreciate the feedback.
Profile ID: LFWR-SCP-O-432206