DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices

Easily testable logical networks based on a 'widened long flip-flop'

Effect of Thread Level Parallelism on the Performance of Optimum Architecture for Embedded Applications

Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders

Efficient implementation of GALS systems over commercial synchronous FPGAs: a new approach

Efficient Network for Non-Binary QC-LDPC Decoder

Elastic Fidelity: Trading-off Computational Accuracy for Energy Reduction

Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach

Energy-Aware Routing for E-Textile Applications

Evaluation and Design Space Exploration of a Time-Division Multiplexed NoC on FPGA for Image Analysis Applications

Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

Evolutionary Optimization in Code-Based Test Compression

Exact Cover with light

Exploiting Real-Time FPGA Based Adaptive Systems Technology for Real-Time Sensor Fusion in Next Generation Automotive Safety Systems

Exploiting Semiconductor Properties for Hardware Trojans

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique

Exposing Software Defined Radio Functionality To Native Operating System Applications via Virtual Devices

Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

Fast and Generalized Polynomial Time Memory Consistency Verification

Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip